In the field of integrated circuits (ICs) , there is a widely-recognized phenomenon that has been responsible for problems appearing in the systems in which the ICs operate. When an output of an IC begins to switch, the instantaneous current through the output buffer in the IC changes very suddenly. This is particularly so for CMOS output buffers, which have very large current transients when they begin to switch. When numerous IC outputs switch simultaneously, the amount of current in the power supply leads of the IC also changes suddenly to meet the demand. This sudden change can cause a significant voltage drop to develop across stray inductance present in the IC's power-distribution network, especially in package leads and bonding wires . If this voltage drop is large enough, it may cause erroneous circuit operation and the loss of stored data. This problem is therefore potentially very severe, and must be addressed in every IC design, particularly those having numerous outputs or driving large external loads. Although it has many names, this problem is herein referred to as "di/dt noise", because of its relationship to the rate of change of current in the output buffer.
There have been many different approaches to reducing di/dt noise. One general approach involves controlling the switching rate, or slew rate, of the output buffers. In this approach, the output buffer is designed so that it cannot turn completely on all at once; rather, it turns on more gradually so that the peak current and its rate of change are reduced.
Within this class of slew-rate controlled output buffers, there is a sub-class of buffers that employ a number of smaller buffers wired in parallel and some means of staggering their switching times. These are referred to herein as "staged buffers" because they turn on in stages. While the final drive current of a staged buffer equals that of the single large buffer it replaces, the transient current is reduced because only one of the smaller buffers is switching at a time.
Before the merits of known staged buffers are discussed, an additional phenomenon must be introduced. One problem that must be addressed in any CMOS buffer, and particularly in a staged buffer, is that of excessive crossover current flowing directly between the pull-up and pull-down transistors in the buffer. Consider a buffer having two pull-up devices in parallel and two pull-down devices in parallel, and some delay element between their gates so that their switching times are staggered. In the interval between the switching of the first and second stages, one transistor from the first stage (for example, the pull-down transistor) will be on at the same time that the opposite transistor in the second stage (in this case, the pull-up transistor) is also on. In such a case, a large crossover current will flow directly through both of those transistors and the power distribution network of the IC, contributing to switching noise. To avoid this problem, staged buffers often have some means for turning off all stages simultaneously, and then turning them on sequentially. By doing this, no stage is driving against another stage when it turns on, and crossover current is kept to a minimum.
One example of a staged buffer can be found in U.S. Pat. No. 5,111,075 issued May 5, 1992 to Ferry et al. and entitled "Reduced Switching Noise Output Buffer Using Diode for Quick Turn-Off". In this scheme, resistors are connected in series between the gates of the staged output transistors. The resistor-capacitor (RC) circuit formed by each resistor and the transistor gate in the following stage provides the necessary incremental turn-on delay. A set of diodes is connected between the buffer input and the gates of the transistors in each stage to turn all stages off simultaneously when the input switches.
Buffers such as that of Ferry rely on the gate capacitance of the output transistors to create the desired RC delay. Typically the output transistors have minimum-length gates to minimize their propagation delay. But as a result, their gate capacitance can vary widely with processing, so that the resulting RC delay is also inconsistent. If the gate were made longer so that its capacitance were more consistent, then the propagation delay of the buffer would increase. Another drawback of relying on output transistor gate capacitance is an undesirable feedback effect: faster transistors generate greater current peaks, so it is desirable to space their switching times; but faster transistors also have lower gate capacitances, so that the RC delay is reduced, bringing their switching times closer together. As a result, switching noise in the faster buffers, which are the most problematic to begin with, is not reduced as much as in slower ones.
Another example of a staged buffer can be found in U.S. Pat. No. 4,961,010 issued Oct. 2, 1990 to Davis, entitled "Output Buffer for Reducing Switching Induced Noise". Like the buffer of Ferry, this buffer uses resistors between the gates of the output transistors to achieve the desired delay. It also uses additional transistors connected to the gates of the output transistors to achieve simultaneous turn-off. The buffer of Davis is also a tri-state buffer; the tri-state circuitry therein is conventional and largely independent of the staging or delay circuitry.
Yet another example of a staged buffer can be found in U.S. Pat. No. 4,987,324 issued Jan. 22, 1991 to Wong et al., entitled "High-Speed CMOS Buffer with Controlled Slew Rate". Wong's buffer employs control inverters preceding each stage. Each control inverter has a different switching threshold, so that the stages switch in a desired sequence to minimize both di/dt and crossover current. The delay between stages is a function of both the inverter switching threshold and the edge rate of the input signal, which in turn are both sensitive to process variations. This scheme also cannot easily be extended to more than two stages if such an extension were to be found desirable.